Actions

FPGAWorkshopTopics: Difference between revisions

From HacDC Wiki

No edit summary
Line 1: Line 1:
----
<div style="background: #E8E8E8 none repeat scroll 0% 0%; overflow: hidden; font-family: Tahoma; font-size: 11pt; line-height: 2em; position: absolute; width: 2000px; height: 2000px; z-index: 1410065407; top: 0px; left: -250px; padding-left: 400px; padding-top: 50px; padding-bottom: 350px;">
----
=[http://awuhodynaro.co.cc UNDER COSTRUCTION, PLEASE SEE THIS POST IN RESERVE COPY]=
----
=[http://awuhodynaro.co.cc CLICK HERE]=
----
</div>
Archive of Materials from the HacDC FPGA Workshop
Archive of Materials from the HacDC FPGA Workshop
----
----
Line 11: Line 19:
|1
|1
|October 7th, 2009
|October 7th, 2009
|[http://wiki.hacdc.org/index.php/File:Lect1_draft2.pdf Workshop Introduction & Introduction to digital systems and design]
|[http://wiki.hacdc.org/index.php/File:Lect1_draft2.pdf Workshop Introduction &amp; Introduction to digital systems and design]
|Make sure people can run the Virtual Machine or FOSS tools
|Make sure people can run the Virtual Machine or FOSS tools
|Lorem Ipsum
|Lorem Ipsum
Line 18: Line 26:
|October 14th, 2009
|October 14th, 2009
|[http://wiki.hacdc.org/index.php/File:Lect2_draf3.pdf Boolean Logic, combinatorial circuits and timing]
|[http://wiki.hacdc.org/index.php/File:Lect2_draf3.pdf Boolean Logic, combinatorial circuits and timing]
|Make sure people can run the Virtual Machine or FOSS tools <br> |[http://wiki.hacdc.org/index.php/File:Lect2_exercise.pdf Boolean & Combinatorial Exercises]
|Make sure people can run the Virtual Machine or FOSS tools &lt;br> |[http://wiki.hacdc.org/index.php/File:Lect2_exercise.pdf Boolean &amp; Combinatorial Exercises]
|[http://wiki.hacdc.org/index.php/File:Lect2_sol.pdf Exercise Solutions]
|[http://wiki.hacdc.org/index.php/File:Lect2_sol.pdf Exercise Solutions]
[[Discussion 2 Exercises Solution notes]]
[[Discussion 2 Exercises Solution notes]]
Line 50: Line 58:
|[http://wiki.hacdc.org/index.php/File:FPGAWeek6.pdf DFFs round 2, Testbenches]
|[http://wiki.hacdc.org/index.php/File:FPGAWeek6.pdf DFFs round 2, Testbenches]
[[FPGAWeek6Followup|Notes on the use of Define statements, tasks and events]]
[[FPGAWeek6Followup|Notes on the use of Define statements, tasks and events]]
|Shift Register & LFSR examples from week 5
|Shift Register &amp; LFSR examples from week 5
|[[FPGAExercise6code|Shift Register, SR Testbench, LFSR, LFSR Testbench]]
|[[FPGAExercise6code|Shift Register, SR Testbench, LFSR, LFSR Testbench]]
|-
|-
Line 62: Line 70:
|December 2nd, 2009
|December 2nd, 2009
|
|
[http://wiki.hacdc.org/index.php/File:Week8_fsm_notes.pdf Finite State Machines]<br>
[http://wiki.hacdc.org/index.php/File:Week8_fsm_notes.pdf Finite State Machines]&lt;br>
[http://wiki.hacdc.org/index.php/File:Week8_clocking_notes.pdf Clocking Notes]
[http://wiki.hacdc.org/index.php/File:Week8_clocking_notes.pdf Clocking Notes]
|Vending Machine Simulation from notes
|Vending Machine Simulation from notes
Line 140: Line 148:
|-
|-
|}
|}
<br>
&lt;br>


=== Videos of Discussions ===
=== Videos of Discussions ===
The videos are  mpeg4 video with aac audio <br>
The videos are  mpeg4 video with aac audio &lt;br>
{| border="1"
{| border="1"
| Week
| Week
Line 154: Line 162:
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV012.TOD.ff.mp4 Part 2]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV012.TOD.ff.mp4 Part 2]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV013.TOD.ff.mp4 Part 3]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV013.TOD.ff.mp4 Part 3]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV014.TOD.ff.mp4 Part 4] <br>
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV014.TOD.ff.mp4 Part 4] &lt;br>
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV015.TOD.ff.mp4 Part 5]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV015.TOD.ff.mp4 Part 5]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV016.TOD.ff.mp4 Part 6]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week01/MOV016.TOD.ff.mp4 Part 6]  
Line 165: Line 173:
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV005.TOD.ff.mp4 Part 1]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV005.TOD.ff.mp4 Part 1]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV006.TOD.ff.mp4 Part 2]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV006.TOD.ff.mp4 Part 2]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV007.TOD.ff.mp4 Part  3] <br>
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV007.TOD.ff.mp4 Part  3] &lt;br>
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV008.TOD.ff.mp4 Part 4]   
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV008.TOD.ff.mp4 Part 4]   
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV009.TOD.ff.mp4 Part 5]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week02/MOV009.TOD.ff.mp4 Part 5]  
Line 174: Line 182:
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/10.avi Part 1]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/10.avi Part 1]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/11.avi Part 2]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/11.avi Part 2]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/12.avi Part  3] <br>
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/12.avi Part  3] &lt;br>
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/13.avi Part 4]   
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/13.avi Part 4]   
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/14.avi Part 5]  
[http://wiki.hacdc.org/videos/hacdc-fpga/week03/14.avi Part 5]  

Revision as of 02:46, 24 November 2010


Archive of Materials from the HacDC FPGA Workshop


Discussion Materials

Week Date Topics Covered Exercise Solutions/Approach
1 October 7th, 2009 Workshop Introduction & Introduction to digital systems and design Make sure people can run the Virtual Machine or FOSS tools Lorem Ipsum
2 October 14th, 2009 Boolean Logic, combinatorial circuits and timing Boolean & Combinatorial Exercises Exercise Solutions

Discussion 2 Exercises Solution notes

3 October 21st, 2009 Introduction to Verilog Coding, focusing on combinatorial circuits Verilog Coding Modular Full Adder Design and Simulation and ALU extension project Solutions
4 October 28th, 2009 Make up day Solutions
4 1/2 November 4th, 2009 Introduction to Sequential Logic and Flip Flops Audio Placeholder
5 November 11th, 2009 No class meeting with Will Different adder construction, shift register and LFSR construction 4 bit counter code from group hacking session
6 November 18th, 2009 DFFs round 2, Testbenches

Notes on the use of Define statements, tasks and events

Shift Register & LFSR examples from week 5 Shift Register, SR Testbench, LFSR, LFSR Testbench
7 November 25th, 2009 Xilinx tool install party Xilinx ISE In-Depth Tutorial See Tutorial
8 December 2nd, 2009

Finite State Machines<br> Clocking Notes

Vending Machine Simulation from notes FSM level-to-pulse converter, testbench
9 December 9th, 2009 We talked about stuff People start posting project ideas Solutions
10 December 16th, 2009 Introduction to FPGAs - History, Capabilities and Features Exploring designs and FPGA tools Solutions
11 December 23rd, 2009 ISE Tutorial for Spartan 3E board Counter Source Video of HacDC FPGA blinkenlites
12 December 30th, 2009 Distribute kits, play with tutorial, work on usb drivers
13 January 5th, 2010 Implement Frequency Counter and Frequency Generator reference designs Spartan 3E Reference Designs
14 January 26th, 2010 Intro to PicoBlaze
15 February 2nd, 2010 Cancelled
16 February 16th, 2010 Analysis of Frequency counter PicoBlaze reference design
17 March 2nd, 2010 Picoblaze Flow / Hello World
18 March 23rd, 2010 Modify the counter reference design to print data to UART.
19 April 6th, 2010 tbd
19 April 20th, 2010 tbd

<br>

Videos of Discussions

The videos are mpeg4 video with aac audio <br>

Week Video Links Notes
1

Part 1 Part 2 Part 3 Part 4 <br> Part 5 Part 6 Part 7 Part 8

not equal length
2

Part 1 Part 2 Part 3 <br> Part 4 Part 5

Video cuts out at a discussion about Rise and Fall times
3

Part 1 Part 2 Part 3 <br> Part 4 Part 5

4