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This is made for the [[FPGA_Workshop|Digital Design and FPGA workshop]] run in Fall 2009.
This is made for the [[FPGA_Workshop|Digital Design and FPGA workshop]] run in Fall 2009.
<br>
&lt;br>
== makefile ==
== makefile ==
Assumptions: You have iverilog, vvp and gtkwave in your $PATH.  iverilog and vvp are the Icarus Verilog package.  gtkwave is the GTKWave+ package.
Assumptions: You have iverilog, vvp and gtkwave in your $PATH.  iverilog and vvp are the Icarus Verilog package.  gtkwave is the GTKWave+ package.
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* Change the TESTBENCH macro to include your verilog testbench.
* Change the TESTBENCH macro to include your verilog testbench.
* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.
* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.
<br>
&lt;br>
The posted makefile shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).
The posted makefile shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).
<pre>
&lt;pre>
###############################################################################
###############################################################################
#
#
# ICARUS VERILOG & GTKWAVE MAKEFILE
# ICARUS VERILOG &amp; GTKWAVE MAKEFILE
# MADE BY WILLIAM GIBB FOR HACDC
# MADE BY WILLIAM GIBB FOR HACDC
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# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
# "make check" - compiles your verilog design - good for checking code
# "make check" - compiles your verilog design - good for checking code
# "make simulate" - compiles your design+TB & simulates your design
# "make simulate" - compiles your design+TB &amp; simulates your design
# "make display" - compiles, simulates and displays waveforms
# "make display" - compiles, simulates and displays waveforms
#  
#  
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display: $(TBOUTPUT)
display: $(TBOUTPUT)
$(VIEWER) $(TBOUTPUT) &
$(VIEWER) $(TBOUTPUT) &amp;
#MAKE DEPENDANCIES
#MAKE DEPENDANCIES
$(TBOUTPUT): $(COUTPUT)
$(TBOUTPUT): $(COUTPUT)
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$(COUTPUT): $(TESTBENCH) $(SRC)
$(COUTPUT): $(TESTBENCH) $(SRC)
$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)
$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)
</pre>
&lt;/pre>


== convenient file copy script ==
== convenient file copy script ==
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Convenient file to copy the makefile from ~/resources/makefile to your current directory.  copy the script into a file, chmod +x the file and place the file in your $PATH.  this assumes that ~/resources/makefile does not have write permissions granted to it.
Convenient file to copy the makefile from ~/resources/makefile to your current directory.  copy the script into a file, chmod +x the file and place the file in your $PATH.  this assumes that ~/resources/makefile does not have write permissions granted to it.


<pre>
&lt;pre>
#!/bin/bash
#!/bin/bash
#
#
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echo "You don't have the makefile at $fileofjustice"
echo "You don't have the makefile at $fileofjustice"
fi
fi
</pre>
&lt;/pre>


[[Category:FPGAWorkshop]]
[[Category:FPGAWorkshop]]

Revision as of 08:17, 24 November 2010


This is made for the Digital Design and FPGA workshop run in Fall 2009. <br>

makefile

Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.

In order to use this makfile, the TOOL INPUT section must be modified to match your needs. This involves the following

  • Change the SRC macro to include your verilog source code files.
  • Change the TESTBENCH macro to include your verilog testbench.
  • Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.

<br> The posted makefile shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu). <pre>

  1. ICARUS VERILOG & GTKWAVE MAKEFILE
  2. MADE BY WILLIAM GIBB FOR HACDC
  3. [email protected]
  4. USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
  5. "make check" - compiles your verilog design - good for checking code
  6. "make simulate" - compiles your design+TB & simulates your design
  7. "make display" - compiles, simulates and displays waveforms
  8. CHANGE THESE THREE LINES FOR YOUR DESIGN
  9. TOOL INPUT

SRC = alu.v alu_func.v alu_regn.v dff.v TESTBENCH = alu_tb.v TBOUTPUT = waves.lxt #THIS NEEDS TO MATCH THE OUTPUT FILE #FROM YOUR TESTBENCH

  1. BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
  2. TOOLS

COMPILER = iverilog SIMULATOR = vvp VIEWER = gtkwave

  1. TOOL OPTIONS

COFLAGS = -v -o SFLAGS = -v SOUTPUT = -lxt #SIMULATOR OUTPUT TYPE

  1. TOOL OUTPUT

COUTPUT = compiler.out #COMPILER OUTPUT

  1. MAKE DIRECTIVES

check : $(TESTBENCH) $(SRC) $(COMPILER) -v $(SRC)

simulate: $(COUTPUT) $(SIMULATOR) $(SFLAGS) $(COUTPUT) $(SOUTPUT)

display: $(TBOUTPUT) $(VIEWER) $(TBOUTPUT) &

  1. MAKE DEPENDANCIES

$(TBOUTPUT): $(COUTPUT) $(SIMULATOR) $(SOPTIONS) $(COUTPUT) $(SOUTPUT)

$(COUTPUT): $(TESTBENCH) $(SRC) $(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC) </pre>

convenient file copy script

Convenient file to copy the makefile from ~/resources/makefile to your current directory. copy the script into a file, chmod +x the file and place the file in your $PATH. this assumes that ~/resources/makefile does not have write permissions granted to it.

<pre>

  1. !/bin/bash
  2. William Gibb
  3. Written for HacDC Digital Design and FPGA workshop
  4. variables!

fileofjustice=~/resources/makefile

  1. script it up!

echo "Copying iVerilog makfile" if [ -r $fileofjustice ]; then cp $fileofjustice . chmod u+w ./makefile echo "makefile copied" else echo "You don't have the makefile at $fileofjustice" fi </pre>