FPGA Workshop: Difference between revisions

Revision as of 16:31, 27 September 2009

Main Topics

1) Introduction to digital logic & design
2) Verilog HDL modeling & testing
3) FPGA's & using them.

Hardware

We'll be covering some FPGA specific topics and projects using real hardware. The first half of the workshop will cover logic design, implementation and testing. This will allow people to put off ordering any hardware until they know that they actually want to pursue FPGA development, since the dev board I've chosen for this is not cheap but I feel is robust enough to be a good starting board for this group.

The hardware we'll be using is the Xilinx Spartan 3AN development kit. This kit is available from a few vendors for 199USD + shipping. This will be discussed more later on. The kit includes programming cable, and evaluation copies of some of the Xilinx tools."

Tools

Verilog Simulation and Waveform Viewing

Icarus verilog & gtkwave; for doing Verilog compilation, simulation and waveform viewing. A makefile has been made to simplify the flow for any exercises and projects we use these tools with. That makefile can be found here.

FPGA Toolchain

After we finish up with covering Verilog modeling, we'll move to the Xilinx ISE Webpack tools and actual work with FPGAs. This software is available from Xilinx for free, and is available for Windows and Linux platforms. This will be used for Verilog compilation, simulation, synthesis of designs, design mapping, place and routing of designs, bitstream generation and board programming.

Virtual Machine

An OpenSuse Virtual Machine (VMWare based) will be available for people to use in this course, if they wish. This will have the icarus verilog tools and GTKwave loaded on it, along with Firefox and OpenOffice. The suseStudio team has encouraged the use of their VMs in such a manner (teaching workshops). This is being built in susestudio, and will be available as a live install as well.
When we move over to the Xilinx tools, people will have to download and install the Xilinx tools by themselves, since that material is copyrighted. Instructions will be given for doing that.

Lecture

Lecture/Discussions will mainly be based on content from a pair of courses in MIT's Opencourseware initiative. This content is licensed on the Creative Commons Attribution NonCommercial Share-alike 3.0 license; as a result, the electronic content generated by the workshop will also need to be made available under the same license.

A video archive will be made available for those unable to attend.

List of Lectures

This is currently an incomplete list - wgibb

Week	Date	Topics Covered	Exercise
1	September 30th, 2009	Workshop Introduction & Introduction to digital systems and design	Make sure people can run the Virtual Machine or FOSS tools
2	October 7th, 2009	Boolean Logic, combinatorial circuits and timing	Make sure people can run the Virtual Machine or FOSS tools
3	October 14th, 2009	Introduction to Verilog Coding, focusing on combinatorial circuits	Verilog Coding - Modular Full Adder Design and Simulation
4	October 21st, 2009	Digital Arithmetic and adder styles	Implement various adders, static gate delays & modeling their timing effects
5	October 28th, 2009	Introduction to Sequential Logic and Flip-Flops	Modeling & Simulation of Flip Flops and simple Sequential Logic
6	TBD	Finite State Machines & You	Modeling of Finite State machines
7	TBD	More on FSM's	Practical FSM Exercise

Workshop Instructor

William Gibb, mad scientist. For contacting him regarding the workshop, please email williamgibb+fpgaworkshop AT g m a i l D0t com [make the domain look like a real address]. Please use plus addressing to ensure a timely response to your message.

References

Grateful Dead Tree References

Fundamentals of Digital Logic with Verilog Design by Brown and Vranesic
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog by Lee
FPGA Prototyping using Verilog Examples by Chu.

These texts will not be required for the course, but are very good launching points for the topics that we are covering.

Online References

@@ Line 74: / Line 74: @@
 == References ==
-=== Dead Tree References ===
+=== Grateful Dead Tree References ===
 Fundamentals of Digital Logic with Verilog Design by Brown and Vranesic <br>
 Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog by Lee <br>
 FPGA Prototyping using Verilog Examples by Chu. <br> <br>
 These texts will not be required for the course, but are very good launching points for the topics that we are covering.
 === Online References ===
 ==== FPGA Vendors ====