Iverilogmakefile: Difference between revisions
From HacDC Wiki
Williamgibb (talk | contribs) (New page: Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package. In order to use this makfile, the TOOL I...) |
Williamgibb (talk | contribs) No edit summary |
||
Line 5: | Line 5: | ||
* Change the TESTBENCH macro to include your verilog testbench. | * Change the TESTBENCH macro to include your verilog testbench. | ||
* Change the TBOUTPUT macro to the name of the file your dumping your testbench output too. | * Change the TBOUTPUT macro to the name of the file your dumping your testbench output too. | ||
<br> | |||
This is made for the Digital Design and FPGA workshop run in Fall 2009. | This is made for the Digital Design and FPGA workshop run in Fall 2009. | ||
<br> | |||
The posted code shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu). | |||
<pre> | <pre> | ||
############################################################################### | ############################################################################### |
Revision as of 13:51, 23 September 2009
Assumptions: You have iverilog, vvp and gtkwave in your $PATH. iverilog and vvp are the Icarus Verilog package. gtkwave is the GTKWave+ package.
In order to use this makfile, the TOOL INPUT section must be modified to match your needs. This involves the following
- Change the SRC macro to include your verilog source code files.
- Change the TESTBENCH macro to include your verilog testbench.
- Change the TBOUTPUT macro to the name of the file your dumping your testbench output too.
This is made for the Digital Design and FPGA workshop run in Fall 2009.
The posted code shows the TOOL INPUT macros pre-populated for targeting an Arithmetic Logic Unit (alu).
############################################################################### # # ICARUS VERILOG & GTKWAVE MAKEFILE # MADE BY WILLIAM GIBB FOR HACDC # [email protected] # # USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE # "make check" - compiles your verilog design - good for checking code # "make simulate" - compiles your design+TB & simulates your design # "make display" - compiles, simulates and displays waveforms # ############################################################################### # # CHANGE THESE THREE LINES FOR YOUR DESIGN # #TOOL INPUT SRC = alu.v alu_func.v alu_regn.v dff.v TESTBENCH = alu_tb.v TBOUTPUT = waves.lxt #THIS NEEDS TO MATCH THE OUTPUT FILE #FROM YOUR TESTBENCH ############################################################################### # BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE ############################################################################### #TOOLS COMPILER = iverilog SIMULATOR = vvp VIEWER = gtkwave #TOOL OPTIONS COFLAGS = -v -o SFLAGS = -v SOUTPUT = -lxt #SIMULATOR OUTPUT TYPE #TOOL OUTPUT COUTPUT = compiler.out #COMPILER OUTPUT ############################################################################### #MAKE DIRECTIVES check : $(TESTBENCH) $(SRC) $(COMPILER) -v $(SRC) simulate: $(COUTPUT) $(SIMULATOR) $(SFLAGS) $(COUTPUT) $(SOUTPUT) display: $(TBOUTPUT) $(VIEWER) $(TBOUTPUT) & #MAKE DEPENDANCIES $(TBOUTPUT): $(COUTPUT) $(SIMULATOR) $(SOPTIONS) $(COUTPUT) $(SOUTPUT) $(COUTPUT): $(TESTBENCH) $(SRC) $(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)